1. Field of the Invention
The present invention relates to a fabrication method of semiconductor memory device, and more particularly, to a fabrication method of a semiconductor memory device in which "punch-through" is prevented from occurring effectively.
2. Description of the Prior Art
Conventionally, with a semiconductor Read-Only Memory (ROM) device, a shorter Turn Around Time (TAT) tends to be required. To respond this requirement, it is preferably that a data-writing or coding process step is arranged as near the final process step of the fabrication sequence as possible.
For example, with a NAND-type semiconductor ROM device, a coding process step of doping impurity into channel areas of MOS transistors in specified memory cells is generally arranged after a process step of forming gate electrodes of the MOS transistors.
A conventional fabrication process sequence of the NAND-type semiconductor ROM device is described below referring to FIGS. 1A to 1E.
An n-type well 102 and a p-type well 103 are formed within a p-type silicon substrate 101. Then, a field oxide film 104 is selectively formed on the substrate 101 to define active regions. A silicon dioxide (SiO.sub.2) film 116 is selectively formed on the active regions to protect the surfaces thereof.
Subsequently, as shown in FIG. 1A, a first photoresist film 106 is formed on the substrate 101 to cover the memory cell area P and the peripheral circuit are P of the substrate 101, and is patterned to have windows 106a. The windows 106a are placed at positions corresponding to the MOS transistors or memory cells to be doped with p-type impurity ions for threshold adjustment in the peripheral circuit area P, respectively.
Using the first photoresist film 106 thus patterned as a mask, boron (B) ions are selectively implanted into the active regions for the n-channel MOS transistors in the peripheral circuit area P at an acceleration energy of about 30 keV with a dose of about 2.0.times.10.sup.12 ions/cm.sup.2. Thus, p-type implantation regions 107 are formed in the p-type well 103, as shown in FIG. 1A. The first photoresist film 106 is then removed.
Similarly, as shown in FIG. 1B, a second photoresist film 108 is formed on the substrate 101 to cover the memory cell area P and the peripheral circuit are P of the substrate 101, and is patterned to have windows 108a. The windows 108a are placed at positions corresponding to the MOS transistors to be doped with p-type impurity ions for threshold adjustment in the peripheral circuit area P.
Using the second photoresist film 108 thus patterned as a mask, boron (B) ions are selectively implanted into the active regions for the p-channel MOS transistors in the peripheral circuit area P at an acceleration energy of about 30 keV with a dose of about 2.0.times.10.sup.12 cm.sup.-2. Thus, p-type implantation regions 109 are formed in the n-type well 102, as shown in FIG. 1B. The second photoresist film 108 is then removed.
Thus, the process steps for adjusting the threshold voltages of the MOS transistors in the peripheral circuit area P are finished.
Next, the substrate 101 thus ion-implanted is thermally oxidized so that a gate oxide film 105 is selectively formed on the respective active regions exposed by removing the silicon dioxide film 116, as shown in FIG. 1C.
A conductive film such as polysilicon film is then formed on the gate oxide film 105 and the field oxide film 104, and is patterned. Thus, gate electrodes 110 are formed over the p-type implantation layers 109 and 107 in the n- and p-type wells 102 and 103 in the peripheral circuit area P, respectively. Also, gate electrodes 110-1, 110-2, 110-3, 110-4 and 110-5 are formed at intervals over the p-type well 103 in the memory cell area C.
The gate electrodes 110, 110-1, 110-2, 110-3, 110-4 and 110-5 are about 0.3 .mu.m in thickness.
To form n-type source/drain regions 111 in the p-type well 103, arsenic (As) ions as an n-type dopant are selectively implanted into the active regions for the n-channel MOS transistors in both the peripheral circuit area P and those in the memory cell area C at an acceleration energy of about 70 keV with a dose of about 3.0.times.10.sup.15 ions/cm.sup.2, respectively.
Thereafter, to form p-type source/drain region 112 in the n-type well 102, boron ions as a p-type dopant are selectively implanted into the active regions for the p-channel MOS transistors in the peripheral circuit area P at an acceleration energy of about 70 keV with a dose of about 5.0.times.10.sup.15 ions/cm.sup.2.
Thus, as shown in FIG. 1D, the n- and p-channel MOS transistors are obtained in the peripheral circuit area P. The n-channel MOS transistors are obtained in the memory cell area C.
The data-writing or coding process is carried out as follows:
As shown in FIG. 1D, a third photoresist film 113 is formed on the substrate 101 on the substrate 101 to cover the memory cell area P and the peripheral circuit are P, and is patterned to have windows 113a. The windows 113a are placed at positions corresponding to the n-channel MOS transistors or memory cells to be coded in the memory cell area C. Here, the windows 113a are positioned over the gate electrodes 110-1, 110-3 and 110-5, respectively.
Using the third photoresist film 113 thus patterned as a mask, phosphorus (P) ions as n-type dopant ions are selectively implanted into the active regions for the MOS transistors to be coded at an acceleration energy of about 360 keV with a dose of about 5.0.times.10.sup.13 ions/cm.sup.2. Thus, n-type implantation regions 114 for coding are formed in the p-type well 103, as shown in FIG. 1E.
Pairs of the n-type implantation regions 114 are formed in self align to the corresponding gate electrodes 110-1, 110-3 and 110-5, respectively. As shown in FIG. 1D, each pair of the regions 114 are communicated with each other under the corresponding gate electrodes 110-1, 110-3 and 110-5.
The third photoresist film 113 is then removed.
Subsequently, as shown in FIG. 1E, an interlayer insulator film 115 is formed to cover the memory cell area C and the peripheral circuit area P.
Then, the substrate 101 thus ion-implanted is subjected to heat-treatment. During this heat-treatment, the n-type dopant atoms doped into the n-type implantation regions 114 diffuse vertically and laterally in the p-type well 103.
As a result, as shown in FIG. 2, due to the punch-through phenomenon, the channel areas of the uncoded MOS transistors or memory cells corresponding to the gate electrodes 110-2 and 110-4 tend to communicate with each other, so that such the uncoded or unwritten memory cells easily become equivalent to the coded or written memory cells.
Thus, with the conventional fabrication method described above, there is a problem that the given, written data or program are easily read out in error since the uncoded memory cells easily become equivalent to the coded memory cells.
Also, since the p-type implantation regions 107 and 109 for threshold adjustment are formed using the different photoresist films 106 and 108, necessary fabrication process steps for this process increase. This is not preferable for such the memory device requiring a shorter TAT.
In addition, another conventional fabrication method of a semiconductor memory device of this sort is disclosed in the Japanese Patent Publication No. 59-121877. This method, however, relates to the memory device of the Metal-Insulator-Semiconductor (MIS) type.